The advantages of monitoring, testing and measuring static current through CMOS and MOS circuits of IC devices are now well documented. The level of static current or quiescent current variously referred to as IDDQ or ICCQ can be used to identify defective IC devices or devices likely to fail. Such static current testing provides substantially greater accuracy than traditional logical testing by voltage measurements, sometimes referred to as "stuck at fault" testing or functional testing.
IDDQ is the current that flows through a CMOS or MOS circuit from the high potential power rail VCC or VDD to the low potential power rail GND when all nodes are quiescent following switching transition events. Ideally, the static current should be zero. But, the less than ideal physical reality of structural conditions across an IC device result in a measurable static current flow from the high potential power rail VDD or VCC through various defect paths to the ground rail GND. Such defect paths are caused for example by gate oxide shorts between the source or drain and gate of MOS transistors, poly bridges and metal bridges between separate nodes, PN junction leakage, mobile ion contamination, "punch through" between source and drain, etc.
If the collective static current through defective paths exceeds an acceptable threshold current level selected for example in the range of 1 .mu.A to 3 .mu.A, the part can be identified as defective or likely to fail even though the part passes traditional logical function tests. An acceptable level or threshold of IDDQ may be selected within a wider range according to the wafer fabrication process. A recent study by Steven D. McEuen, "IDDQ BENEFITS", Ford Microelectronics Inc. 9965 Federal Drive, Colorado Springs, CO 80921, published in 1991 IEEE VLSI Test Symposium, Paper 14.1, pp 285-290, found that static current testing afforded over 50% greater effectiveness compared to traditional logical function testing in eliminating defective parts from the "good population". This dramatic increase in reliability and accuracy provided by IDDQ monitoring and current testing is confirmed by Tom Storey and Wojceich Maly, Carnegie Melon University, Pittsburgh, PA, USA and John Andrews and Myron Miske, National Semiconductor Corporation, South Portland, ME USA in the paper "Comparing Stuck Fault and Current Testing via CMOS Chip Test" published at the European Test Conference, Apr. 1991. IDDQ monitoring appears to be essential for approaching the goal of "Zero Defect" parts.
A disadvantage of static current testing with external automatic test equipment (ATE) is that such testers introduce substantial parasitic capacitance and inductive reactance increasing the time to quiescent conditions following switching events and slowing the rate of IDDQ testing. Static current measurement is made after a test vector is applied at selected inputs to the part. As many as 40 to several hundred different test vectors may be applied to the part followed by IDDQ measurements. Ideally the testing should be accomplished at a test frequency of at least 0.1 MHz and greater, for example 1 MHz. To achieve such test frequencies the foregoing studies recommend the use of so-called built-in current monitors (BIC) fabricated on the chip to reduce parasitic capacitance, inductance, and consequent delays.
Such a built-in current sensing circuit is described by M. Patyra and W. Maly, Carnegie Mellon University, Pittsburgh, PA, 15213 in the paper "Circuit Design for Built-In Current Testing" IEEE 1991 Custom Integrated Circuit Conference. The basic circuit concept is illustrated in FIG. 1 which is adapted from that paper. BIC sensors 10 monitor the amount of quiescent current in the ground lines of the CMOS functional units or modules 20 under test. As shown in FIG. 1 the basic structure of the BIC 10 includes a voltage drop device VDROP coupled between the CMOS circuit module 20 and the ground rail GND, and a voltage comparator VCOMP.
Each clock cycle the BIC monitor circuit 10 compares the virtual ground voltage VGND above VDROP with a voltage reference VREF. VREF is chosen so that VGND&lt;VREF for defect free acceptable parts. For VGND&gt;VREF, the quiescent current exceeds an acceptable threshold level and a fail signal F flags the CMOS circuit portion as defective.
A detailed circuit implementation of the BIC 10 is illustrated in FIG. 2. The voltage drop device VDROP is provided by bipolar transistor Q1. The comparator VCOMP is provided by MOS transistors M1-M7 and includes a current mirror that establishes VREF from a reference current IREF. The circuit implementation also includes a two stage amplifier M3,M8,I1, a NAND gate N1 and bistable edge sensitive latch LATCH, and a circuit breaker M9,M10,I2. The latch LATCH generates a fail flag signal F with a logic value "1" for a failure indication when VGND&gt;VREF. The output value of F equals "0" for a no fault indication. The circuit breaker M9,M10,I2 also disconnects the failed CMOS circuit module or macrocell 20 from the ground rail GND.
A disadvantage of the Patyra and Maly BIC and similar built-in static current monitors, is the impact of the BIC on normal system operation of the part. The BIC circuit introduces an inevitable impedance in the ground path of the IC device with accompanying degradation of system function which cannot be eliminated. While Patyra and Maly seek to minimize the impact of the BIC sensor on circuit performance, the residual voltage drop across bipolar transistor Q1 remains.
Another example of a BIC circuit is described by A. Welbers et al., Philips Research Laboratories, P.O. Box 8000, 5600 J. A., Eindhoven, The Netherlands in a paper "A Built-In CMOS IDD Quiescent Monitor Circuit". However this BIC circuit is available for static current testing only during the manufacturing and testing phases. It is then apparently permanently bypassed by hard wiring and is not available for test use during the life of the chip.
The present invention seeks to overcome the degradation of system function caused by built-in current monitor and sensor circuits in the normal operation of IC devices. In order to accomplish this result, the present invention makes novel use of a standard test access port such as the IEEE Standard 1149.1 TAP. While it has been suggested that the built-in current monitor BIC may be combined with a boundary scan testing test access port TAP, this has been only for the purpose of applying test vectors for static current measurement using the boundary scan register of the test access port.
The test access port TAP defined by IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture and JTAG Version 2.0 Protocol for incorporation on an integrated circuit chip is illustrated in FIG. 3. At least four pins of the IC device and a varying percentage of the chip silicon surface area are dedicated to the test access port and associated TAP circuits. The TAP is intended to standardize and facilitate boundary scan testing and other design specific testing of the IC device while the chip is still mounted on a circuit board and without separate test instrumentation. The TAP permits all phases of testing with access at all pins of the IC device through boundary scan principles even for surface mount devices and without the necessity of "bed of nails" physical contact. Access to all pins for testing is achieved electronically through the boundary scan shift register, one of the test data registers of the test access port.
The dedicated pins for the test access port include a test data input (TDI) pin to receive data signals for the test data registers (TDRs) and to receive instruction codes for the test instruction register (TIR). The test data output (TDO) pin shifts out data signals from the TDRs and instruction codes from the TIR for example for input to the TDI pin of the next IC device on a circuit board. IEEE Standard 1149.1 compliant chips of a circuit board may be coupled with boundary scan registers in series in a "daisy chain" forming a selected test ring for test mode select functions. Data signals and instruction codes are shifted out from the TDRs and TIR to the TDO pin through respective multiplexers MUX, a latch or passgate, and an output buffer coupled to the TDO pin.
The remaining two required pins of the standard TAP are a test mode select (TMS) pin and a test clock (TCK) pin which provide respective control and clock signals to the TAP controller which in turn directs operation of the test access port. In response to TMS control signals and TCK clock signals, the TAP controller selects either the instruction register TIR for entry of an instruction code from the TDI pin, or selects a test data register (TDR) for entry of data signals from the TDI pin. According to the selected mode of operation, for example a test to be performed or a design specific procedure to be followed, the appropriate instruction code is shifted into the instruction register (TIR). The instruction code is decoded by instruction decode register (IDR) and the TIR selects one or more of the test data registers (TDRs) required for the selected test or procedure.
The minimum required TDRs include the boundary scan register TDR1 for performing boundary scan testing and the bypass register TDR2 for bypassing data signals and instruction codes to the TDO pin in order to bypass a particular chip for a selected test or other procedure. The test logic may also include design specific TDRs such as TDR4 illustrated in FIG. 3 for performing a customized or design specific test or system logic procedure. An optional TAP test logic reset (TRST,) pin may be dedicated for an asynchronous resetting of the TAP controller.
The central operating feature of the standard TAP is the boundary scan register TDR1 shown in more detail in FIG. 4. The boundary scan register TDR1 is a shift register of series coupled boundary scan cells (BSC). A boundary scan cell BSC is coupled at each pin of the IC device in the system logic path between the respective input or output pin and the IC device internal system logic. Under appropriate program control, data signals may be shifted into position through the boundary scan path of the boundary scan register for example for input to the IC device system logic at the input pins. The processed data signals may be latched at the boundary scan cells adjacent to output pins to be shifted out through the boundary scan path and TDO pin for test analysis. Each boundary scan cell (BSC) generally incorporates two flip-flops and two multiplexers for accomplishing these boundary scan test objectives. The boundary scan register and boundary scan test principles permit access to all pins of the IC device without physical contact by a "bed of nails" testing apparatus.
A more detailed fragmentary block diagram of the test access port data registers TDRs is illustrated in FIG. 5. FIG. 5 shows a bank of TDRs including the minimum required boundary scan register TDR1 and bypass register TDR2. An optional test data register is the device identification register TDR3 for coded identification of a device name. Additionally there may be a plurality of specialized design specific test data registers TDR4, TDR5 and TDRN etc. for design specific tests or procedures.
A state diagram showing the operation of the TAP controller for a standardized test access port is illustrated in FIG. 6. The TAP controller is an "n" state finite state machine, in this case a 16 state finite state machine composed of four flip flops which in combination determine the 16 states of the TAP controller. While inactive, the TAP controller remains in the Test Logic Reset state or condition. The TAP controller is held in this state as long as the TMS signal is logic high level 1 or the TRST* signal is logic low level o.
When the TMS pin changes from 1 to 0, a test procedure is initiated with transition to the Run Test/Idle state. From the Run Test/Idle condition, the TAP controller selects either the TAP test instruction register TIR or one of the TAP test data registers TDRs for shifting respective instruction codes or data signals into and from the captured register TDRN between the TDI and TDO pins. In the state diagram of FIG. 6, the binary digits accompanying the flow chart arrows represent the TMS signal. The indicated transition occurs for the specified value of the TMS signal at the next rising edge of a clock signal TCK. As used herein, the Test Logic Reset (TLR) state of the TAP controller is referred to as the inactive state. All other states of the TAP controller state diagram are referred to as the active state or active states.
Further background information and detailed instruction on the construction and operation of standardized test access ports are found in the following references: IEEE STANDARD TEST ACCESS PORT AND BOUNDARY SCAN ARCHITECTURE, Test Technology Technical Committee of the IEEE Computer Society, Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017 USA (May 21, 1990) (IEEE Standard 1149.1-1990); Colin M. Maunder and Rodham E. Tulloss, THE TEST ACCESS PORT AND BOUNDARY SCAN ARCHITECTURE, IEEE Computer Society Press Tutorial, IEEE Computer Society Press, 10662 Los Vaqueros Circle, P.O. Box 3014, Los Alamitos, Calif. 90720-1264 (IEEE 1990); John Andrews, "IEEE Standard Boundary Scan 1149.1", National Semiconductor Corporation, 333 Western Avenue, South Portland, Me. 04106, a paper delivered at WESCON, San Francisco, 1991.
As noted by Maunder and Tulloss, the design specific TAP test data registers (TDRs) can be part of the on-chip system logic or the test logic and can have both system and test functions. The dedicated test access port pins afford convenient access to the chip for example from a portable computer at an external location for testing or otherwise servicing the IC device in situ in its operating circuit board and environment.
According to the terminology adopted in this specification, the reference to the test access port or TAP includes the test logic as well as the dedicated pins of the TAP. The reference to "test" components and elements of the TAP is generalized to "TAP" components and elements to encompass both test logic functions and system logic functions for which the TAP might be used. Thus, the standard test data input pin, test data output pin, test mode select pin, test clock pin, test data registers, and test instruction register etc. may also be referred to herein more generally as TAP data input (TDI) pin, TAP data output (TDO) pin, TAP mode select (TMS) pin, TAP clock (TCK) pin, TAP test data registers (TDRs), and TAP instruction register (TIR) etc. This more generalized terminology is appropriate to objects and features of the present invention for implementation of the TAP components and elements whether used for test functions or design specific system logic functions of an IC device.